A single 8-point fast 1D-DCT is used to calculate the DCT coefficient values of the host image and the watermark image to minimize the resource utilization and power consumption. Parallelism techniques are employed in block level in order to achieve high performance. The proposed architecture has a 12–stage pipeline. Mathematical model is developed to reduce the computational complexity for the calculation of embedding and scaling factors, which are used to make the resultant image of best quality with uniform watermark visibility. In this watermarking process, 1D-DCT is introduced to facilitate hardware implementation. In this article, a novel block-based visible image watermark VLSI architecture design and its hardware implementation in field programmable gate array (FPGA) is proposed. Performance analysis results are measured using image processing metrics. The proposed watermarking schemes are robust against various types of attacks such as Gaussian noise, shearing, scaling, rotation, flipping, affine transform, signal processing and JPEG compression. Here, directsequence code division multiple access approach is used to embed multibit text information in DCT and DWT transform domains. The result of watermarking scheme is suitable for public watermarking applications, where the original image is not available for watermark extraction. The normalisation procedure is invariant to affine transform attacks.

The watermarking approach is based on image normalisation in which both watermark embedding and extraction are carried out with respect to an image normalised to meet a set of predefined moment criteria. We present a technique for irreversible watermarking approach robust to affine transform attacks in camera, biomedical and satellite images stored in the form of monochrome bitmap images.

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